As interface speeds increase, jitter in integrated circuits is consuming an increasing portion of timing margins. Minimizing jitter is a significant design consideration. Jitter is manifested as the peak to peak noise, i.e. voltage fluctuation, on a signal. One cause of jitter is noise on the voltage supply rails. Noise on the voltage supply rails is often traced back to variation in the current consumption by on-die components. Circuits consume dynamic power whenever logic toggles, i.e., change values between 0 and 1, and most of the current consumption occurs during toggling. When the current consumption increases during toggling, the power supply voltage tends to fall. After toggling, the current consumption decreases and the power supply voltage eventually reverts back to the specified voltage. Typical current transients are significantly faster than the time constant of the power distribution network of the integrated circuit. This means that the current through the supply inductance will not change quickly enough in response to a loading change in the circuit to prevent either a voltage sag or a voltage spike. A high frequency ripple can be seen to occur at the clock rate of the circuit in response to the increased current consumption immediately after toggling.
The control of jitter is currently being addressed primarily through the use of decoupling capacitors. An increasing amount of die area is spent accommodating the decoupling capacitors used to limit the magnitude of voltage fluctuation on the power supply in an effort to reduce the amount of jitter. Any software techniques that can minimize the amount of jitter would have the benefit of reducing jitter with reduced area overhead.
It is in this context that embodiments of the invention arise.